====== Simatic S7 SCL reference: Bit logic operations ======

Back to reference overview: [[de:s7:scl_reference|Simatic S7 SCL reference with examples]]

===== positive / negative edge monitoring =====
{{anchor:edge_monitor}}
Of course, there is an R_TRIG / F_TRIG function for edge monitoring, but do you really have to call an FB and an IDB for such a simple function?

Both negative and positive edge monitoring require an extra BOOL type static, db, or mark variable (temp is not good!) in addition to the signal variable. In this variable, the signal state one cycle earlier is stored and the current state of the signal is compared.
If the old state is FALSE and the current state is TRUE, then a positive edge is received; if the reverse is true, the old state is TRUE and the new state is FALSE.

The example below illustrates the two options, the variables in this case being FB local "static" variables, but they can also be DB variables or markers. The signal can also be an input:

<code SCL>
// signal, old_signal is type BOOL

IF #signal AND NOT (#old_signal) THEN
    // positive flash block program
    // 
    ;
END_IF;

IF NOT(#signal) AND #old_signal THEN
    // negative flash block program
    // 
    ;
END_IF;

// update the storage BOOL
#old_signal := #signal;
</code>


===== R_TRIG =====
Detect __positive__ signal edge, if the state change from FALSE to TRUE at CLK. I have described above a similar but much simpler procedure for edge monitoring: [[de:s7:scl_reference_bit_logic#edge_monitor|positive / negative edge monitoring]].

See: [[de:s7:scl_reference#bit_logic|Bit logic operations]]

<color white/orange>[[de:s7:tia_knowhow#fc|_FB_]]</color>  
**R_TRIG**
(<color blue>CLK := </color> signal monitoring ([[de:s7:tia_datatypes#bool|BOOL]]),
<color blue>Q => </color> result ([[de:s7:tia_datatypes#bool|BOOL]]);

^parameter name^parameter type^function|
|<color blue>CLK </color>|input|Incoming signal|
|<color blue>Q </color>|output|Result of edge evaluation|

===== F_TRIG =====
Detect __negative__ signal edge, if the state change from TRUE to FALSE at CLK. I have described above a similar but much simpler procedure for edge monitoring: [[de:s7:scl_reference_bit_logic#edge_monitor|positive / negative edge monitoring]].

See: [[de:s7:scl_reference#bit_logic|Bit logic operations]]

<color white/orange>[[de:s7:tia_knowhow#fc|_FB_]]</color>  
**F_TRIG**
(<color blue>CLK := </color> signal monitoring ([[de:s7:tia_datatypes#bool|BOOL]]),
<color blue>Q => </color> result ([[de:s7:tia_datatypes#bool|BOOL]]);

^parameter name^parameter type^function|
|<color blue>CLK </color>|input|Incoming signal|
|<color blue>Q </color>|output|Result of edge evaluation|

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